Power-saving means is widely used to minimize power consumption in a computer system. Many kinds and levels of power-saving modes are developed to achieve the purpose. One of the examples is so-called as ACPI. ACPI (Advanced Configuration and Power Management Interface) is a specification defining standard interfaces for hardware configuration and power management of the power-saving means. According to the ACPI specification, the central processing unit (CPU) of the computer system operates in various power states, e.g. C1, C2, C3, etc. Different power states result in different levels of power saving effects. For any power-saving mechanism, it is important to reduce power consumption while providing a stable operational environment for circuit at a relatively low temperature.
Generally speaking, the power management for the CPU of the computer system is implemented with the south bridge chip of the chipset. Referring to a conventional computer scheme of FIG. 1, for activating and deactivating power-saving modes, the south bridge chip 2 includes a stop clock control module 20 coupled to the CPU 1 and north bridge chip 3, and an interrupt controller 22 coupled to the stop clock control module 20 and one or more peripheral equipment, e.g. peripheral device 4.
When the operating system (OS) of the computer system is to enter a power-saving state, the CPU 1 issues a sleep command to the south bridge chip 2. In response to the sleep command, the stop clock control module 20 of the south bridge chip 2 asserts a stop clock signal STPCLK# to the CPU 1 via a clock signal pin 21. Once the STPCLK# signal is generated, the CPU 1 issues a stop grant signal STPGNT to the south bridge chip 2 via the north bridge chip 3 through data buses connecting thereto. In response to the STPGNT signal, the CPU 1, as well as the entire computer system, enters the power-saving state so as to reduce power consumption.
Afterwards, the CPU 1 need be awaked when interrupted by any of the peripheral devices. For example, in response to the receipt of an interrupt signal issued by the peripheral device 4 via the interrupt signal pin 40, the interrupt controller 22 of the south bridge chip 2 issues a wake-up signal to trigger the stop clock control module 20 of the south bridge chip 2 to de-assert the STPCLK# signal. Thus, the CPU 1 and the entire computer system are awaked to recover to the normal operation state.
With the increasing number and variety of peripheral devices and highly advance of computer's performance, new and diverse architectures of computer systems have been developed. For example, as shown in FIG. 2, peripheral equipment such as second peripheral device 6 can be connected to the north bridge chip 3 other than the south bridge chip 2. However, the computer system cannot process interrupts from the second peripheral device 6 via the north bridge chip 3 even though a second interrupt controller 50 can be disposed between the second peripheral device 6 and north bridge chip 3 if the second interrupt controller 50 is implemented with a programmable interrupt controller (PIC). Nowadays, an input/output advanced programmable interrupt controller (IO APIC) has been developed for solving interrupt routing efficiency issues. Unfortunately, interrupts from the second peripheral device 6 are still unable to wake up the CPU or computer system in the C2/C3 mode of the ACPI specification to do interrupt service even if the second interrupt controller 50 is implemented with an IO APIC.